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1 1-megabit 2.7-volt only dataflash ? AT45DB011B features ? single 2.7v - 3.6v supply serial peripheral interface (spi) compatible 20 mhz max clock frequency page program operation ? single cycle reprogram (erase and program) ? 512 pages (264 bytes/page) main memory supports page and block erase operations one 264-byte sram data buffer continuous read capabili ty through entire array ? ideal for code shadowing applications fast page program time ? 7 ms typical 120 s typical page to buffer transfer time low power dissipation ? 4 ma active read current typical ? 2 a cmos standby current typical hardware data protection feature 100% compatible with at45db011 commercial and industri al temperature ranges green (pb/halide-free) packaging options description the AT45DB011B is a 2.7-volt only, serial interface flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. its 1,081,344 bits of memory are organized as 512 pages of 264 bytes each. in addi- tion to the main memory, the AT45DB011B also contains one sram data buffer of 264 bytes. the buffer allows receiving of data while a page in the main memory is being reprogrammed. eeprom emulation (bit or byte alterability) is easily handled with a self-contained three step read-modify-write operation. unlike conventional flash memories that are accessed randomly with multiple address lines and a parallel inter- face, the dataflash uses a spi serial interface to sequentially access its data. spi mode 0 and mode 3 are suppor ted. the simple serial in terface facilitates hardware AT45DB011B preliminary 16- megabit 2.7-volt only serial dataflash pin configurations pin name function cs chip select sck serial clock si serial input so serial output wp hardware page write protect pin reset chip reset rdy/busy ready/busy cbga top view through package a b c 123 vcc wp reset gnd rdy/bsy si sck cs so tssop top view ty p e 1 1 2 3 4 5 6 7 14 13 12 11 10 9 8 rdy/busy reset wp vcc gnd sck so cs nc nc nc nc nc si soic 1 2 3 4 8 7 6 5 si sck reset cs so gnd vcc wp rev. 1984h?dflsh?10/04
2 AT45DB011B 1984h?dflsh?10/04 layout, increases syst em reliability, minimizes switching noise, and reduces package size and active pin count. the device is optimized for use in many commercial and industrial applica- tions where high density, low pin count, low voltage, and low power are essential. the device operates at clock frequencies up to 20 mhz with a typical active read current consumption of 4ma. to allow for simple in-system reprogrammability, the AT45DB011B does not require high input voltages for programming. the device operates from a single power supply, 2.7v to 3.6v, for both the program and read operations. the AT45DB011B is enabled through the chip select pin (cs ) and accessed via a three-wire interface consisting of the serial input (si), serial out- put (so), and the serial clock (sck). all programming cycles are self-timed, and no separate erase cycle is required before programming. when the device is shipped from atmel, the most significant page of the memory array may not be erased. in other words, the contents of the last page ma y not be filled with ffh. block diagram memory array to provide optimal flexibility, th e memory array of the AT45DB011B is divided into three levels of granularity comprising of sectors, blocks , and pages. the memory architecture diagram illustrates the breakdown of each level and details the number of pages per sector and block. all program operations to the dataflash occur on a page by page basis; however, the optional erase operations can be performed at the block or page level. flash memory array page (264 bytes) buffer (264 bytes) i/o interface sck cs reset vcc gnd rdy/busy wp so si
3 AT45DB011B 1984h?dflsh?10/04 memory architecture diagram device operation the device operation is controlled by instructions from the host processor. the list of instruc- tions and their associated opcodes are contained in tables 1 through 4 (pages 11 and 12). a valid instruction starts with the falling edge of cs followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. while the cs pin is low, toggling the sck pin controls the loading of the opcode and the desired buffer or main memory address location through the si (serial input) pin. all instructions, addresses, and data are transferred with the most significant bit (msb) first. buffer addressing is referenced in the datasheet using the terminology bfa8-bfa0 to denote the nine address bits required to designate a byte address within a buffer. main memory addressing is referenced using the terminology pa8-pa0 and ba8-ba0 where pa8-pa0 denotes the 10 address bits required to designate a page address and ba8-ba0 denotes the nine address bits required to designate a byte address within the page. read commands by specifying the appropriate opcode, data can be read from the main memory or from the data buffer. the dataflash supports two categories of read modes in relation to the sck sig- nal. the differences between the modes are in respect to the inactive state of the sck signal as well as which clock cycle data will begin to be output. the two categories, which are com- prised of four modes total, are defined as inactive clock polarity low or inactive clock polarity high and spi mode 0 or spi mode 3. a separate opcode (refer to table 1 on page 11 for a complete list) is used to select which category will be used for reading. please refer to the ?detailed bit-level read timing? diagrams in this datasheet for details on the clock cycle sequences for each mode. block = 2112 bytes (2k + 64) 8 pages block 0 block 1 block 2 block 62 block 63 block 61 page = 264 bytes (256 + 8) page 0 page 1 page 6 page 7 page 8 page 9 page 510 page 511 block 0 page 14 page 15 page 16 page 17 page 18 page 509 block 1 block architecture page architecture sector 0 = 2112 bytes (2k + 64) sector 1 = 65,472 bytes (62k + 1984) sector architecture sector 2 = 67,584 bytes (64k + 2k) block 3 block 29 block 30 block 31 block 32 block 33 block 34 sector 1 sector 2 sector 0
4 AT45DB011B 1984h?dflsh?10/04 continuous array read: by supplying an initial starting address for the main memory array, the continuous array r ead command can be utilized to s equentially read a continuous stream of data from the device by simply pr oviding a clock signal; no additional addressing information or control signals need to be provided. the dataflash incorporates an internal address counter that will automatically incremen t on every clock cycle, allowing one continu- ous read operation without the need of additional address sequences. to perform a continuous read, an opcode of 68h or e8h must be clocked into the device followed by 24 address bits and 32 don?t care bits. the first six bits of the 24-bit address sequence are reserved for upward and downward compatibility to larger and smaller density devices (see notes under ?command sequence for read/write operations? diagram). the next nine address bits (pa8-pa0) specify which page of the main memory array to read, and the last nine bits (ba8-ba0) of the 24-bit address s equence specify the starting byte address within the page. the 32 don?t care bits that follow the 24 address bits are needed to initialize the read operation. following the 32 don?t care bits, additional clock pu lses on the sck pin will result in serial data being output on the so (serial output) pin. the cs pin must remain low during the loading of the opcode, the address bits, the don?t care bits, and the reading of data. when the end of a page in main memory is reached during a continuous array read, the devic e will continue readi ng at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). when the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. as with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. a low-to-high transition on the cs pin will terminate the read operat ion and tri-state the so pin. the maximum sck frequency allowable for the continuous array read is defined by the f car specification. the continuous array read bypasses both data buffers and leaves the contents of the buffers unchanged. main memory page read: a main memory read allows the user to read data directly from any one of the 512 pages in the main memory, bypassing the data buffer and leaving the con- tents of the buffer unchanged. to start a page read, the 8-bit opcode, 52h or d2h, must be clocked into the device followed by 24 address bits and 32 don?t care bits. in the AT45DB011B, the first six address bits are reserved for larger density devices (see notes on page 15), the next nine address bits (pa8-pa0) specify the page address, and the next nine address bits (ba8-ba0) specify the starting byte address within the page. the 32 don?t care bits which follow the 24 address bits are sent to initialize the read operation. following the 32 don?t care bits, additional pulses on sck result in serial data being output on the so (serial output) pin. the cs pin must remain low during the loading of the opcode, the address bits, and the reading of data. when the end of a page in main memory is reached during a main memory page read, the device will continue reading at the beginn ing of the same page. a low- to-high transition on the cs pin will terminate the read oper ation and tri-state the so pin. buffer read: data can be read from the data buffer using an opcode of 54h or d4h. to perform a buffer read, the eight bits of the opcode must be followed by 15 don?t care bits, nine address bits, and eight don?t care bits. since the buffer size is 264 bytes, nine address bits (bfa8- bfa0) are required to specify the first byte of data to be read from the buffer. the cs pin must remain low during the loading of the opcode, the address bits, the don?t care bits, and the reading of data. when the end of the buffer is reached, the device will continue reading back at the beginning of the buffer. a low-to-high transition on the cs pin will terminate the read operation and tri-state the so pin.
5 AT45DB011B 1984h?dflsh?10/04 status register read: the status register can be used to determine the device?s ready/busy status, the result of a main memory page to buffer compare operation, or the device density. to read the status register, an opcode of 57h or d7h must be loaded into the device. after the last bit of the opcode is shifted in, the eight bits of the status register, starting with the msb (bit 7), will be shifted out on th e so pin during the next eight clock cycles. the five most significant bits of th e status register will contain device in formation, while the remain- ing three least significant bits are reserved fo r future use and will have undefined values. after bit 0 of the status register ha s been shifted out, the sequence will repeat itself (as long as cs remains low and sck is being toggled) starting again with bit 7. the data in the status register is constantly upda ted, so each repeating se quence will output new data. ready/busy status is indicated using bit 7 of the status register. if bit 7 is a 1, then the device is not busy and is ready to accept the next command. if bit 7 is a 0, then the device is in a busy state. the user can continuously poll bit 7 of the status register by stopping sck at a low level once bit 7 has been output. the status of bit 7 will continue to be output on the so pin, and once the device is no longer busy, the state of so will change from 0 to 1. there are eight operations which can cause the device to be in a busy state: main memory page to buffer transfer, main memory page to buffer compare, buffer to main memory page program with built-in erase, buffer to main memory page program without built-in erase, page erase, block erase, main memory page program, and auto page rewrite. the result of the most recent main memory page to buffer compare operation is indicated using bit 6 of the status register. if bit 6 is a 0, then the data in the main memory page matches the data in the buffer. if bit 6 is a 1, then at least one bit of the data in the main memory page does not match the data in the buffer. the device density is indicated using bits 5, 4, 3 and 2 of the status register. for the AT45DB011B, the four bits are 0, 0, 1 and 1. the decimal value of these four binary bits does not equate to the device density; the three bits represent a combinational code relating to dif- fering densities of serial dataflash devices, allowing a total of sixteen different density configurations. program and erase commands buffer write: data can be shifted in from the si pin into the data buffer. to load data into the buffer, an 8-bit opcode of 84h is followed by 15 don?t care bits and nine address bits (bfa8-bfa0). the nine address bits specify the first byte in the buffer to be written. the data is entered following the address bits. if the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer. data will continue to be loaded into the buffer until a low-to-high transit ion is detected on the cs pin. buffer to main memory page program with built-in erase: data written into the buffer can be programmed into the main memory. an 8-bit opcode of 83h is followed by the six reserved bits, nine addre ss bits (pa8-pa0) that specify the page in the main memory to be written, and nine additional don?t care bits. when a low-to-high transition occurs on the cs pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory. both the erase and the programming of the page are internally self-timed and should take place in a maximum time of t ep . during this time, the status regist er will indicate that the part is busy. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rdy/busy comp0011xx
6 AT45DB011B 1984h?dflsh?10/04 buffer to main memory page program without built-in erase: a previously erased page within main memory can be programmed with the contents of the buffer. an 8-bit opcode of 88h is followed by the six reserved bits, nine address bits (pa8-pa0) that specify the page in the main memory to be written, and nine additional don?t care bits. when a low-to- high transition occurs on the cs pin, the part will prog ram the data stored in the buffer into the specified page in the main memory. it is necessary that the page in main memory that is being programmed has been previously erased. the pr ogramming of the page is internally self- timed and should take place in a maximum time of t p . during this time, t he status register will indicate that the part is busy. successive page programming operations without doing a page erase are not recommended. in other words, changing bytes within a page from a ?1? to a ?0? during multiple page program- ming operations without erasing that page is not recommended. page erase: the optional page erase command can be used to individually erase any page in the main memory array allowing the buffer to main memory page program without built-in erase command to be ut ilized at a later time. to perf orm a page erase, an opcode of 81h must be loaded into the device, followed by six reserved bits, nine address bits (pa8- pa0), and nine don?t care bits. the nine address bits are used to specify which page of the memory array is to be erased. when a low-to-high transition occurs on the cs pin, the part will erase the selected page to 1s. the erase operation is internally self-timed and should take place in a maximum time of t pe . during this time, the status regi ster will indicate that the part is busy. block erase: a block of eight pages can be erased at one time allowing the buffer to main memory page program wit hout built-in erase command to be utilized to reduce programming times when writing large amounts of data to the device. to perform a block erase, an opcode of 50h must be loaded into the device, followed by six reserved bits, six address bits (pa8- pa3), and 12 don?t care bits. the six address bits are used to specify which block of eight pages is to be erased. when a low-to-high transition occurs on the cs pin, the part will erase the selected block of eight pages to 1s. the erase operation is internally self-timed and should take place in a maximum time of t be . during this time, the status register will indicate that the part is busy. block erase addressing pa8 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa 0 bl ock 000000xxx0 000001xxx1 000010xxx2 000011xxx3 111100xxx60 111101xxx61 111110xxx62 111111xxx63
7 AT45DB011B 1984h?dflsh?10/04 main memory page program through buffer: this operation is a combination of the buffer write and buffer to main memory page program with built-in erase operations. data is first shifted into the buffer from the si pin and then programmed into a specified page in the main memory. an 8-bit opcode of 82h is followed by the six reserved bits and 18 address bits. the nine most significant address bits (pa8-pa0) select the page in the main memory where data is to be written, and the next nine address bits (bfa8-bfa0) select the first byte in the buffer to be written. after all address bits are shifted in, the part will take data from the si pin and store it in the data buffer. if the end of t he buffer is reac hed, the device will wrap around back to the beginning of the buffer. when there is a low-to-high transition on the cs pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory. both the erase and the programming of the page are internally self timed and should take place in a maximum of time t ep . during this time, the status register will indicate that the part is busy. additional commands main memory page to buffer transfer: a page of data can be transferred from the main memory to buffer. an 8-bit opcode of 53h is followed by the six reserved bits, nine address bits (pa8-pa0) which specify the page in main memory that is to be transferred, and nine don?t care bits. the cs pin must be low while toggling the sck pin to load the opcode, the address bits, and the don?t care bits from the si pin. the transfer of the page of data from the main memory to the bu ffer will begin when the cs pin transitions from a low to a high state. during the transfer of a page of data (t xfr ), the status register can be read to determine whether the transfer has been completed or not. main memory page to buffer compare: a page of data in main memory can be com- pared to the data in the buffer. an 8-bit opcode of 60h is followed by 24 address bits consisting of the six reserved bits, nine address bits (pa8-pa0) which specify the page in the main memory that is to be compared to the buffer, and nine don?t care bits. the loading of the opcode and the address bits is the sa me as described previously. the cs pin must be low while toggling the sck pin to load the opcode, the address bits, and the don?t care bits from the si pin. on the low-to-high transition of the cs pin, the 264 bytes in the selected main mem- ory page will be compared with the 264 bytes in the buffer. during this time (t xfr ), the status register will indicate that the part is busy. on completion of the compare operation, bit 6 of the status register is updated with the result of the compare. auto page rewrite: this mode is only needed if multiple bytes within a page or multiple pages of data are modified in a random fashion. this mode is a combination of two operations: main memory page to buffer transfer and buffer to main memory page program with built-in erase. a page of data is first transferred from the main memory to the data buffer, and then the same data (from the buffer) is programmed back into its original page of main memory. an 8- bit opcode of 58h is followed by the six reserved bits, nine address bits (pa8-pa0) that spec- ify the page in main memory to be rewritten, and nine additional don?t ca re bits. when a low- to-high transition occurs on the cs pin, the part will first transfe r data from the page in main memory to the buffer and then program the data from the buffer back into same page of main memory. the operation is internally self-timed and should take place in a maximum time of t ep . during this time, the status register will indicate that the part is busy. if a sector is programmed or reprogrammed sequentially page by page, then the programming algorithm shown in figure 1 on page 26 is recommended. otherwise, if multiple bytes in a page or several pages are programmed randomly in a sector, then the programming algorithm shown in figure 2 on page 27 is recommended. each page within a sector must be updated/rewritten at least once within every 10,000 cumulative page erase/program opera- tions in that sector.
8 AT45DB011B 1984h?dflsh?10/04 note: 1. after power is applied and v cc is at the minimum specified da tasheet value, the system should wait 20 ms before an opera- tional mode is started. absolute maximum ratings* temperature under bias .... ........... ............ ..... -55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 c to +150 c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v dc and ac operating range AT45DB011B operating temperature (case) com. 0 c to 70 c ind. -40 c to 85 c v cc power supply (1) 2.7v to 3.6v
9 AT45DB011B 1984h?dflsh?10/04 operation mode summary the modes described can be separated into two groups ? modes which make use of the flash memory array (group a) and modes which do not make use of the flash memory array (group b). group a modes consist of: 1. main memory page read 2. main memory page to buffer transfer 3. main memory page to buffer compare 4. buffer to main memory page program with built-in erase 5. buffer to main memory page program without built-in erase 6. page erase 7. block erase 8. main memory page program through buffer 9. auto page rewrite group b modes consist of: 1. buffer read 2. buffer write 3. status register read if a group a mode is in progress (not fully completed), then another mode in group a should not be started. however, during this time in which a group a mode is in progress (other than main memory page read), status register read from group b can be started. furthermore, during page erase and block erase operation in progress from group a, any of the modes from group b can be started. pin descriptions serial input (si): the si pin is an input-only pin and is used to shift data into the device. the si pin is used for all data input, including opcodes and address sequences. serial output (so): the so pin is an output-only pin and is used to shift data out from the device. serial clock (sck): the sck pin is an input-only pin and is used to control the flow of data to and from the dataflash. data is always clocked into the device on the rising edge of sck and clocked out of the devi ce on the falling edge of sck. chip select (cs ): the dataflash is selected when the cs pin is low. when the device is not selected, data will not be accepted on the si pin, and the so pin will remain in a high- impedance state. a high-to-low transition on the cs pin is required to start an operation, and a low-to-high transition on the cs pin is required to end an operation. write protect: if the wp pin is held low, the first 256 pages of the main memory cannot be reprogrammed. the only way to reprogram the first 256 pages is to first drive the protect pin high and then use the program commands previously mentioned. if this pin and feature are not utilized it is re commended that the wp pin be driven high externally.
10 AT45DB011B 1984h?dflsh?10/04 reset : a low state on the reset pin (reset ) will terminate the operation in progress and reset the internal state machine to an idle state. the device will remain in the reset condition as long as a low level is present on the reset pin. normal operation can resume once the reset pin is brought back to a high level. the device incorporates an internal power-on rese t circuit, so there are no restrictions on the reset pin during power-on sequenc es. if this pin and feature are not utilized it is recom- mended that the reset pin be driven high externally. ready/busy : this open-drain output pin will be driv en low when the device is busy in an internally self-timed o peration. this pin, which is normally in a high state (through a 1k ? exter- nal pull-up resistor), will be pulled low during programming operations, compare operations, and during page-to-buffer transfers. the busy status indicates that the flash memory array and one of the buffers cannot be accessed; read and wr ite operations to the other buff er can still be performed. power-on/reset state when power is first applied to the device, or when recovering from a reset condition, the device will default to spi mode 3. in addition, the so pin will be in a high-impedance state, and a high-to-low transition on the cs pin will be required to start a valid instruction. the spi mode will be automatically selected on every falling edge of cs by sampling the inactive clock state. after power is applied and v cc is at the minimum datasheet value, the system should wait 20 ms before an operational mode is started. system considerations dataflash is controlled by the serial clock (sck) and chip select (cs ) pins. these signals must rise and fall monotonically and be free from noise. excessive noise or ringing on these pins can be misinterpreted as multiple edges and cause improper operation of the device. the pc board traces must be kept to a minimum distance or appropriately terminated. if neces- sary, decoupling capacitors can be added on these pins to provide filtering against noise glitches. as system complexity continues to increase, voltage regulation is becoming more important. a key element of any volt age regulation scheme is it s current sourcing capab ility. like all flash memories, the peak currents for dataflash occur during the programming and erase opera- tions. the peak current during programming or er ase of a dataflash is 70 ma to 80 ma. the regulator needs to supply this peak current requirement. an under specified regulator can cause current starvation. besides increasing system noise, current starvation during program- ming or erase can lead to improper operation and possible data corruption.
11 AT45DB011B 1984h?dflsh?10/04 note: in tables 2 and 3, an sck mode designation of ?any? denotes an y one of the four modes of operation (inactive clock polarit y low, inactive clock polarity high, spi mode 0, or spi mode 3). table 1. read commands command sck mode opcode continuous array read inactive clock polarity low or high 68h spi mode 0 or 3 e8h main memory page read inactive clock polarity low or high 52h spi mode 0 or 3 d2h buffer read inactive clock polarity low or high 54h spi mode 0 or 3 d4h status register read inactive clock polarity low or high 57h spi mode 0 or 3 d7h table 2. program and erase commands command sck mode opcode buffer write any 84h buffer to main memory page program with built-in erase any 83h buffer to main memory page program without built-in erase any 88h page erase any 81h block erase any 50h main memory page program through buffer any 82h table 3. additional commands command sck mode opcode main memory page to buffer transfer any 53h main memory page to buffer compare any 60h auto page rewrite through buffer any 58h
AT45DB011B 12 note: r = reserved bit p = page address bit b = byte/buffer address bit x = don?t care table 4. detailed bit-level addressing sequence opcode opcode address byte address byte address byte additional don?t care bytes required 50h 01010000 rrrrrr pppppp xxxxxxxxxxxx n/a 52h 01010010 rrrrrr ppppppppp bbbbbbbbb 4 bytes 53h 01010011 rrrrrr ppppppppp xxxxxxxxx n/a 54h 01010100 x x x xxxxxxxxxxxx bbbbbbbbb 1 byte 57h 01010111 n/a n/a n/a n/a 58h 01011000 rrrrrr ppppppppp xxxxxxxxx n/a 60h 01100000 rrrrrr ppppppppp xxxxxxxxx n/a 68h 01101000 rrrrrr ppppppppp bbbbbbbbb 4 bytes 81h 10000001 rrrrrr ppppppppp xxxxxxxxx n/a 82h 10000010 rrrrrr ppppppppp bbbbbbbbb n/a 83h 10000011 rrrrrr ppppppppp xxxxxxxxx n/a 84h 10000100 x x x xxxxxxxxxxxx bbbbbbbbb n/a 88h 10001000 rrrrrr ppppppppp xxxxxxxxx n/a d2h 11010010 rrrrrr ppppppppp bbbbbbbbb 4 bytes d4h 11010100 x x x xxxxxxxxxxxx bbbbbbbbb 1 byte d7h 11010111 n/a n/a n/a n/a e8h 11101000 rrrrrr ppppppppp bbbbbbbbb 4 bytes r eserve d r eserve d r eserve d r eserve d r eserve d r eserve d pa8 pa 7 pa6 pa 5 pa 4 pa3 pa2 pa1 pa0 ba 8 ba 7 ba6 ba 5 ba4 ba 3 ba 2 ba1 ba0
13 AT45DB011B 1984h?dflsh?10/04 note: 1. i cc1 during a buffer read is 20ma maximum. dc characteristics symbol parameter condition min typ max units i sb standby current cs , reset , wp = v ih , all inputs at cmos levels 210a i cc1 (1) active current, read operation f = 20 mhz; i out = 0 ma; v cc = 3.6v 4 10 ma i cc2 active current, program/erase operation v cc = 3.6v 10 25 ma i li input load current v in = cmos levels 1 a i lo output leakage current v i/o = cmos levels 1 a v il input low voltage 0.6 v v ih input high voltage 2.0 v v ol output low voltage i ol = 1.6 ma; v cc = 2.7v 0.4 v v oh output high voltage i oh = -100 a v cc - 0.2v v ac characteristics symbol parameter min typ max units f sck sck frequency 20 mhz f car sck frequency for continuous array read 20 mhz t wh sck high time 22 ns t wl sck low time 22 ns t cs minimum cs high time 250 ns t css cs setup time 250 ns t csh cs hold time 250 ns t csb cs high to rdy/busy low 200 ns t su data in setup time 5 ns t h data in hold time 10 ns t ho output hold time 0 ns t dis output disable time 18 ns t v output valid 20 ns t xfr page to buffer transfer/compare time 120 200 s t ep page erase and programming time 10 20 ms t p page programming time 715ms t pe page erase time 610ms t be block erase time 715ms t rst reset pulse width 10 s t rec reset recovery time 1s
14 AT45DB011B 1984h?dflsh?10/04 input test waveforms and measurement levels t r , t f < 3 ns (10% to 90%) output test load ac waveforms two different timing diagrams are shown belo w. waveform 1 shows the sck signal being low when cs makes a high-to-low transition, and wa veform 2 shows the sck signal being high when cs makes a high-to-low transition. both wa veforms show valid timing diagrams. the setup and hold times for the si signal are referenced to the low-to-high transition on the sck signal. waveform 1 shows timing that is also compatible with spi mode 0, and waveform 2 shows timing that is compat ible with spi mode 3. waveform 1 ? inactive clock po larity low and spi mode 0 waveform 2 ? inactive clock polarity high and spi mode 3 ac driving levels ac measurement level 0.45v 2.0 0.8 2.4v device under test 30 pf cs sck si so t css valid in t h t su t wh t wl t csh t cs t v high impedance valid out t ho t dis high impedance cs sck si so t css valid in t h t su t wl t wh t csh t cs t v high z valid out t ho t dis high impedance
15 AT45DB011B 1984h?dflsh?10/04 reset timing (inactive clock polarity low shown) note: the cs signal should be in th e high state before the reset signal is deasserted. command sequence for read/write operati ons (except status register read) notes: 1. ?r? designates bits rese rved for larger densities. 2. it is recommended that ?r? be a logical ?0?. 3. for densities larger than 1m bit, th e ?r? bits become the most significant p age address bit for the appropriate density. cs sck reset so high impedance high impedance si t rst t rec t css si cmd 8 bits 8 bits 8 bits msb reserved for larger densities page address (pa8-pa0) byte/buffer address (ba8-ba0/bfa8-bfa0) lsb r r r r r r x x x x x x x x x x x x x x x x x x
16 AT45DB011B 1984h?dflsh?10/04 write operations the following block diagram and waveforms illustra te the various write sequences available. main memory page program through buffer buffer write buffer to main memory page program (dat a from buffer progra mmed into flash page) flash memory array page (264 bytes) buffer (264 bytes) i/o interface si buffer to main memory page program main memory page program through buffer buffer write si cmd n n+1 last byte completes writing into buffer starts self-timed erase/program operation cs r r , pa8-7 pa6-0, bfa8 bfa7-0 si cmd x xx, bfa8 bfa7-0 n n+1 last byte completes writing into buffer cs si cmd pa6-0, x x cs starts self-timed erase/program operation r r , pa8-7 each transition represents 8 bits and 8 clock c y cles n = 1st byte written n+1 = 2nd byte written
17 AT45DB011B 1984h?dflsh?10/04 read operations the following block diagram and waveforms illustra te the various read sequences available. main memory page read main memory page to buff er transfer (data from fl ash page read into buffer) buffer read flash memory array page (264 bytes) buffer (264 bytes) i/o interface main memory page to buffer main memory page read buffer read so si cmd pa6-0, ba8 ba7-0 x xxx cs n n+1 so r r , pa8-7 si cmd pa6-0, x x starts reading page data into buffer cs so r r , pa8-7 si cmd x xx, bfa8 bfa7-0 cs n n+1 so x each transition represents 8 bits and 8 clock c y cles n = 1st byte read n+1 = 2nd byte read
18 AT45DB011B 1984h?dflsh?10/04 detailed bit-level read timing ? inactive clock polarity low continuous array read (opcode: 68h) main memory page read (opcode: 52h) si 0 1xx cs so sck 12 63 64 65 66 67 68 high-impedance d 7 d 6 d 5 d 2 d 1 d 0 d 7 d 6 d 5 data out bit 0 of page n+1 bit 2111 of page n lsb msb t su t v si 0 1 0 10 xxx cs so sck 12345 60 61 62 63 64 65 66 67 xx high-impedance d 7 d 6 d 5 data out command opcode msb t su t v
19 AT45DB011B 1984h?dflsh?10/04 detailed bit-level read timing ? inac tive clock polarity low (continued) buffer read (opcode: 54h) status register read (opcode: 57h) si 0 1 0 10 xxx cs so sck 12345 36 37 38 39 40 41 42 43 xx high-impedance d 7 d 6 d 5 data out command opcode msb t su t v si 0 1 0 10 111 cs so sck 12345 78910 11 12 16 17 high-impedance d 7 d 6 d 5 status register output command opcode msb t su t v 6 d 1 d 0 d 7 lsb msb
20 AT45DB011B 1984h?dflsh?10/04 detailed bit-level read timing ? inactive clock polarity high continuous array read (opcode: 68h) main memory page read (opcode: 52h) si 0 1xxx cs so sck 12 63 64 65 66 67 high-impedance d 7 d 6 d 5 d 2 d 1 d 0 d 7 d 6 d 5 bit 0 of page n+1 bit 2111 of page n lsb msb t su t v data out si 0 1 0 10 xxx cs so sck 12345 61 62 63 64 65 66 67 xx high-impedance d 7 d 6 d 5 data out command opcode msb t su t v d 4 68
21 AT45DB011B 1984h?dflsh?10/04 detailed bit-level read timing ? inac tive clock polarity high (continued) buffer read (opcode: 54h) status register read (opcode: 57h) si 0 1 0 10 xxx cs so sck 12345 37 38 39 40 41 42 43 xx high-impedance d 7 d 6 d 5 data out command opcode msb t su t v d 4 44 si 0 1 0 10 111 cs so sck 12345 78910 11 12 17 18 high-impedance d 7 d 6 d 5 status register output command opcode msb t su t v 6 d 4 d 0 d 7 lsb msb d 6
22 AT45DB011B 1984h?dflsh?10/04 detailed bit-level read timing ? spi mode 0 continuous array read (opcode: e8h) main memory page read (opcode: d2h) si 1 1xxx cs so sck 12 62 63 64 65 66 67 high-impedance d 7 d 6 d 5 d 2 d 1 d 0 d 7 d 6 d 5 data out bit 0 of page n+1 bit 2111 of page n lsb msb t su t v si 1 1 0 10 xxx cs so sck 12345 60 61 62 63 64 65 66 67 xx high-impedance d 7 d 6 d 5 data out command opcode msb t su t v d 4
23 AT45DB011B 1984h?dflsh?10/04 detailed bit-level read timing ? spi mode 0 (continued) buffer read (opcode: d4h) status register read (opcode: d7h) si 1 1 0 10 xxx cs so sck 12345 36 37 38 39 40 41 42 43 xx high-impedance command opcode t su d 7 d 6 d 5 data out msb t v d 4 si 1 1 0 10 111 cs so sck 12345 78910 11 12 16 17 high-impedance status register output command opcode msb t su 6 d 1 d 0 d 7 lsb msb d 7 d 6 d 5 t v d 4
24 AT45DB011B 1984h?dflsh?10/04 detailed bit-level read timing ? spi mode 3 continuous array read (opcode: e8h) main memory page read (opcode: d2h) si 1 1xxx cs so sck 12 63 64 65 66 67 high-impedance d 7 d 6 d 5 d 2 d 1 d 0 d 7 d 6 d 5 bit 0 of page n+1 bit 2111 of page n lsb msb t su t v data out si 1 1 0 10 xxx cs so sck 12345 61 62 63 64 65 66 67 xx high-impedance d 7 d 6 d 5 data out command opcode msb t su t v d 4 68
25 AT45DB011B 1984h?dflsh?10/04 detailed bit-level read timing ? spi mode 3 (continued) buffer read (opcode: d4h) status register read (opcode: d7h) si 1 1 0 10 xxx cs so sck 12345 37 38 39 40 41 42 43 xx high-impedance d 7 d 6 d 5 data out command opcode msb t su t v d 4 44 si 1 1 0 10 111 cs so sck 12345 78910 11 12 17 18 high-impedance d 7 d 6 d 5 status register output command opcode msb t su t v 6 d 4 d 0 d 7 lsb msb d 6
26 AT45DB011B 1984h?dflsh?10/04 figure 1. algorithm for sequentially programming or reprogramming the entire array notes: 1. this type of algorithm is used for applications in wh ich the entire array is programmed sequentially, filling the array page-by- page. 2. a page can be written using either a main memory page progra m operation or a buffer write operation followed by a buffer to main memory page program operation. 3. the algorithm above shows the programming of a single page . the algorithm will be repeated sequentially for each page within the entire array. start main memory page program (82h) end provide address and data buffer write (84h) buffer to main memory page program (83h)
27 AT45DB011B 1984h?dflsh?10/04 figure 2. algorithm for randomly modifying data notes: 1. to preserve data integrity, each page of a dataflash se ctor must be updated/rewritten at least once within every 10,000 cumulative page erase/program operations within that sector. 2. a page address pointer must be maintained to indicate which page is to be rewritten. the auto page rewrite command must use the address specified by the page address pointer. 3. other algorithms can be used to rewrite portions of the flash array. low-power applications may choose to wait until 10,000 cumulative page erase/program operations have accumulated before rewriting all pages of the sector. see application note an-4 (?using atmel?s serial dataflash?) for more details. start main memory page to buffer transfer (53h) increment page address pointer (2) auto page rewrite (2) (58h) end provide address of page to modify if planning to modify multiple bytes currently stored within a page of the flash array main memory page program (82h) buffer write (84h) buffer to main memory page program (83h) sector addressing pa8 pa7 pa6 pa5 pa4 pa3 pa2 - pa0 s e ct or 000000 x 0 0xxxxx x 1 1xxxxx x 2
28 AT45DB011B 1984h?dflsh?10/04 note: green packages cover lead-free requirements. ordering information f sck (mhz) i cc (ma) ordering code package operation range active standby 20 10 0.01 AT45DB011B-cc AT45DB011B-sc AT45DB011B-xc 9c1 8s2 14x commercial (0 c to 70 c) 20 10 0.01 AT45DB011B-ci AT45DB011B-si AT45DB011B-xi 9c1 8s2 14x industrial (-40 c to 85 c) green package options (pb/halide-free) f sck (mhz) i cc (ma) ordering code package operation range active standby 20 10 0.01 AT45DB011B-su AT45DB011B-xu 8s2 14x industrial (-40 c to 85 c) package type 9c1 9-ball (3 x 3 array), 1.0 mm pitch, 5 x 5 mm plastic chip-scale ball grid array package (cbga) 8s2 8-lead, 0.210" wide, plastic gull wing small outline (eiaj soic) 14x 14-lead, 0.170" wide, plastic thin shrink small outline package (tssop)
29 AT45DB011B 1984h?dflsh?10/04 packaging information 9c1 ? cbga 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 9c1 , 9-ball (3 x 3 array), 5 x 5 x 1.2 mm body, 1.0 mm ball pitch chip-scale ball grid array package (cbga) a 9c1 04/11/01 dimensions in millimeters and (inches). controlling dimension: millimeters. a b c 32 1 2.0 (0.079) 1.50(0.059) ref 0.40 (0.016) dia ball typ 2.0 (0.079) 1.20(0.047)max 0.25(0.010)min 5.10(0.201) 1.00 (0.0394) bsc non-accumulative 4.90(0.193) 5.10(0.201) 4.90(0.193) 1.50(0.059) ref a1 id 1.00 (0.0394) bsc non-accumulative top view side view bottom view
30 AT45DB011B 1984h?dflsh?10/04 8s2 ? eiaj soic 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8s2 , 8-lead, 0.209" body, plastic small outline package (eiaj) 10/7/03 8s2 c common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this drawing is for general information only; refer to eiaj drawing edr-7320 for additional information. 2. mismatch of the upper and lower dies and resin burrs are not included. 3. it is recommended that upper and lower cavities be equal. if they are different, the larger dimension shall be regarded. 4. determines the true geometric position. 5. values b and c apply to pb/sn solder plated terminal. the standard thickness of the solder layer shall be 0.010 +0.010/ ? 0.005 mm. a 1.70 2.16 a1 0.05 0.25 b 0.35 0.48 5 c 0.15 0.35 5 d 5.13 5.35 e1 5.18 5.40 2, 3 e 7.70 8.26 l 0.51 0.85 ? 0? 8? e 1.27 bsc 4 end view side view e b a a1 d e n 1 c e1 ? l top view
31 AT45DB011B 1984h?dflsh?10/04 14x ? tssop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 14x (formerly "14t") , 14-lead (4.4 mm body) thin shrink small outline package (tssop) b 14x 05/16/01 5.10 (0.201) 4.90 (0.193) 1.20 (0.047) max 0.65 (.0256) bsc 0.20 (0.008) 0.09 (0.004) 0.15 (0.006) 0.05 (0.002) index mark 6.50 (0.256) 6.25 (0.246) seating plane 4.50 (0.177) 4.30 (0.169) pin 1 0.75 (0.030) 0.45 (0.018) 0? 8 0.30 (0.012) 0.19 (0.007) dimensions in millimeters and (inches). controlling dimension: millimeters. jedec standard mo-153 ab-1.
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